The Galaga Replay project

All my namco custom chip replacement projects are set up for one goal: porting a Galaga arcade board from Namco/Midway (shown on the picture) to a FPGA.
Porting is done based on the schematics found on the internet, reverse engineering projects for the namco ICs (my own and from others) and a lot of measurements on the real board.

Many thanks to KLOV.COM (manual), Mike (FPGAARCADE.COM - 00xx, 04xx, 07xx custom IC implementations) and Adam (ONECIRCUIT.COM - 02xx custom IC implementations), they were a big help for this task! See my links section to get to their web pages.

The other missing custom parts (06xx, 51xx and 54xx) I have set up by myself. Check out my custom IC project page for details on these parts.

The implementation is based on VHDL, audio/video is fully functional (except star field, see below) and is finally mapped to my arcade replay board.

Here an example (showing only 3 bit RGB using a simple test adapter on a FPGA eval board, but implementation of course generates all):

The starfield setup was somewhat tricky. I do not know any resource explaining the correct content of the 05xx custom IC. For now I set up my own generators producing a similar single-pixel scattering on the screen. Two independent generators using two independent enable signals, generating the required 4 starfield maps. For now I think it looks already really good on a first glance, but it is still not 100% original.

Mike brought to my attention to check out a bootleg to reverse-engineer the 05xx behavior. Luckily I own a Gallag bootleg board as well...

So I started to investigate the LFSR-Register there - I am close to realize a first version of it on my implementation of the video board as well. Let's see if it looks better than mine, although it (may) still not replace the original behavior.

The "state-of the art" setup can be found in MAME: they implemented a LUT-based setup acquired by "reading out" a real 05xx. This solution has still some minor disadvantage: with the real LFSR the stars shifts slowly to the left while the stars are scrolled down. The LUT way would also require an emulation of this behavior as well. So I am also not really a fan of this kind of implementation - it is still not 100% perfect...

I made some significant progress on the 05xx starfield generator - I am about to release the real implementation - see here!

Here a small AVI (you may need a decent player like VLC installed on your system to view it). Again, the video is simplified using a 3 bit RGB output (but of course all bits are there, I'll update the file soon...):

And finally two photographs of the final setup (game/attract mode and test mode), including VGA out on a Nexys 3 board:


Internally I am running following board as well, will be released as soon as the framework of the board is released:

- Spartan 3E-1600, using the Replay Board

The implementation is released as initial/early beta version on these boards:

- Spartan 3E-1200, using the Nexys 2 board from Digilent
- Spartan 6-LX16, using the Nexys 3 board from Digilent

See my links section to get to the Digilent web page. You may also check out the PMODAmp1 there, which I use for the sound output...

You can download the readme file and the binary release for these boards, if you want to try it out.
Yet the binaries do not use the latest 05xx starfield and final namco custom IC setups, I want to keep them for the release of the Replayboard!

Nexys 2
Nexys 3
Nexys 2
test binaries
Nexys 3
test binaries
Download DOC Download DOC Download BIN Download BIN

Due to this much higher complexity (compared to existing implementations of single-CPU games like Frogger, Pacman, ... etc.), this implementation will NOT run on any FPGA smaller than a Spartan3e-1200, a Spartan6-LX16 or similar!
(especially not when also adding proper VGA and sound output)

So please don't ask me if it is possible to set up this game on a Papilio or similar starter board. You need something for real (wo)men! ;-)

Source code:

Actually, I implement this game on the Replay board and won't support the other platforms for now. Thus the downloads above are "as is", without further support and updates.

Although the result works on Spartan 3E and Spartan 6, I'd like to get rid of this issues (so the code should be clean for both architectures) before releasing anything. Unfortunately I have also some other projects in my queue and only limited time for all this topics, so please stay tuned for now. Otherwise I'll flood my spare time also with a lot of beginners questions, that would not make any sense...
I'd only share the code for now if you have experience with FPGA design and if you are willing to support me by fixing this issues, this would definitely speed up things (please contact me and show me some references of your work)!

Some facts (see also utilization of Spartan 3A - using the Trenz TE320 board - on the right):
- fully synchronous implementation, runs with ~6 MHz system clock
- XST synthesis estimates max. speed at ~100MHz (Spartan 3 family)
- separate implementation of CPU and VIDEO board, as the original
- uses several Namco ICs, which are also available as separate CPLD/FPGA projects
- 3x 8bit CPU (Z80)
- 2x 4bit CPU (mb88xx as custom ICs)
- Video: 288x224 pixel, 8bit (3R/3G/2B), H:~16kHz, V:~60Hz
- Sound: one channel sound synthesis, 2 channel noise generation (third channel unused), 8bit output, ~320kS/sec

Not included in this exemplary utilization (but included in the Nexys board setups):
- VGA-out and proper scan-doubler logic/buffer memory
- digital filtering and noise-shaping for 1-bit sound output