Namco 05xx custom IC replacement
The Namco 05xx custom chip is a maximum-length, 16bit LFSR (linear-feedback shift register). Together with video sync
and blanking signals it is used to generate a "starfield" for video games like Bosconian and Galaga.
What is less commonly known, the 05xx has also a PRNG (pseudo-random noise generator) output, which seems not to be used by any game (as far as I know).
My first approach was to use the LFSR from Gallag, a bootleg board - but it is not correct (but looks already quite nice).
Actual implementations (like MAME) use a table-lookup of the starfield. This is not 100% accurate, as the LFSR has the property, that when the stars are "shifted" in x-direction they also do also a slight "shift" in y-direction. This can be also observed when looking at the stars at the left or right edges - they go out of the screen on one side and get in again on the other, the MAME emulation does not do this. This project aims for the correct implementation - which has the advantage that it also fits in a 64-macrocell CPLD device, as no memories for the starfield positions are required.
I used my logic testbench to readout the logic functionality the IC provides.
The tough task was to compare the pattern it produces to all possible (this are 2048) 16bit maximum length LFSR implementations and all possible (65535) init states. As there is some logic on the output, I had to use some kind of "best correlation" test first. Luckily, my PC had some time left to perform this task on the one hand and on the other hand the right polynomial did have a much higher correlation than all the others!
This was quite a brute-force approach, but it worked out. I was able to retreive the correct generator polynomial and the exact start point of the LFSR (which is important to set the start point when we "reset" the IC).
Now it was just required to set up proper logic tables for the RGB output and the output enable signal
I aquired and to match them to the LFSR values from my simulation. I synchronized it exactly counting the
clock cycles after applying the starfield reset signal. This procedure worked out well and I got a 100% match.
Finally I mapped the remaining logic LUTs to simplified equations (and of course I checked again for correctness).
The shifting is implemented by the fact, that the LFSR has 65535 steps and the starfield is 256x256=65536 pixels in size, determined by the x/y synchronization signals.
By shortening and enlarging the synchronization signals (using plain shift registers and some and/or logic) and using that as an enable for the shift register, it is possible to "scroll" the starfield up to 3 pixels in any direction. This is done for the LFSR register only and thus independent of the RGB mapping and output enable generation.
On the left, a figure of the principle implementation is shown.
Namco 05xx implementation and testing
The functionality is coded using VHDL and is implemented on Quartus Web Edition.
It fits easily on the DIL-CPLD replacement ICs (using Altera parts) from MikeJ (see below). As the device is smaller in terms of pinout, it is required to connect pin 12,13 and 14 on the CPLD board and align it in the socket to pin 1. I set up a adapter socket as I didn't want to modify my CPLD board directly (see photo on the right). Of course the pins could be directly soldered on the board to set up a compact replacement for this custom chip (but you do it at your own risk, of course).
I compared the RGB read-outs of the original versus the CPLD design for all maps using my testbench again.
The starfield looks awesome on Galaga as well as on Bosconian, including proper scrolling of course!
I'll provide the binary code for the mentioned CPLD boards on my file area ASAP
(to request access to the file area, take a look at the end of this page).
If you want to purchase such a board, please contact Mike at fpgaarcade.com (see my links section for further details), I don't have these boards for sale (I just got some development setups I re-use for my projects for "in-board verification" of my code).